View AT91R4000805_4286659.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Incorporates the ARM7TDMI(R) ARM(R) Thumb(R) Processor Core
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Little-endian - EmbeddedICETM (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM - 32-bit Data Bus - Single-clock Cycle Access Fully-programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to Eight Chip Selects - Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller - Four External Interrupts, Including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter - Three External Clock Inputs - Two Multi-purpose I/O Pins per Channel Two USARTs - Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features - CPU and Peripheral Can be Deactivated Individually Fully Static Operation - 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range Available in 100-lead TQFP Package -40 C to +85 C Temperature Range
* *
*
AT91 ARM(R) Thumb(R) Microcontrollers AT91R40008 Electrical Characteristics
* * *
* * * * * * * *
1. Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set and very low power consumption. Furthermore, it features 256K bytes of on-chip SRAM and a large number of internally banked registers, resulting in very fast exception handling, and making the device ideal for real-time control applications. The AT91R40008 microcontroller features a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface (EBI). An 8-level priority vectored interrupt controller, in conjunction with the Peripheral Data Controller, significantly improves the real-time performance of the device. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful microcontroller that offers a flexible and high-performance solution to many computeintensive embedded control applications.
1795E-ATARM-12-Dec-05
2. Absolute Maximum Ratings*
Operating Temperature (Industrial) .. -40 C to + 85 C Storage Temperature...................... -60 C to + 150 C Voltage on Any Input Pin with Respect to Ground ..................................................-0.3V to max of VDDIO .......................................................... + 0.3V and 3.6V Maximum Operating Voltage (VDDIO) ....................3.6V Maximum Operating Voltage (VDDCORE) .............1.95V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
3. DC Characteristics
The following characteristics are applicable to the Operating Temperature range: TA = -40 C to +85 C, unless otherwise specified and are certified for a Junction Temperature up to 100 C.
Table 3-1.
Symbol
DC Characteristics
Parameter DC Supply I/Os DC Supply Core Input Low Voltage Input High Voltage Pin Group 1(2): IOL = 16 mA(1) Conditions Min 2.7 1.65 -0.3 2.0 Typ Max 3.6 1.95 0.8 VDDIO + 0 .3 0.4 0.4 0.4 0.2 VDDIO - 0.4 VDDIO - 0.4 VDDIO - 0.4 VDDIO - 0.2 10 VDDIO = 3.6V, VIN = 0V Pin Group 1(2)
(3) (4)
Units V V V V V V V V V
VDDIO
VDDCORE VIL VIH
VOL
Output Low Voltage
Pin Group 2(3): IOL = 8 mA(1) Pin Group 3 : IOL = 2 mA
(2) (4) (1) (1) (1)
All Output Pins: IOL = 0 mA
Pin Group 1 : IOH = 16 mA VOH Output High Voltage
(4)
Pin Group 2(3): IOH = 8 mA(1) Pin Group 3 : IOH = 2 mA
(1) (1)
All Output Pins: IOH = 0 mA ILEAK IPULL Input Leakage Current Input Pull-up Current
A A mA mA mA pF A mA
280 16 8 2 5.3
IOUT
Output Current
Pin Group 2 : Pin Group 3 :
CIN
Input Capacitance
TQFP100 Package VDDIO= 3.6V, VDDCORE = 1.95V, MCKI = 0Hz All Inputs Driven TMS, TCK, TDI, NRST = 1
TA = 25 C TA = 85 C
120 2.3
ISC
Static Current
Notes:
1. IOL = Output Current at low level. IOH= Output Current at high level. 2. Pin Group 1 = NUB/NWR1, NWE/NWR0, NOE/NRD1 3. Pin Group 2 = D0-D15, A0/NLB, A1-A19, P28/A20/CS7, P29/A21/CS6, P30/A22/CS5, P31/A23/CS4, NCS0, NCS1, P26/NCS2, P27/NCS3 4. Pin Group 3 = All Others
3
1795E-ATARM-12-Dec-05
4. Power Consumption
The values in the following tables are values measured in the typical operating conditions (i.e., VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25 C) on the AT91EB40A Evaluation Board and are given as demonstrative values. Table 4-1.
Mode Reset Fetch in ARM mode from internal SRAM All peripheral clocks activated Fetch in ARM mode from internal SRAM All peripheral clocks deactivated Normal Fetch in ARM mode from external SRAM(1) All peripheral clocks deactivated Fetch in Thumb mode from external SRAM(1) All peripheral clocks deactivated All peripheral clocks activated Idle All peripheral clocks deactivated Note: 1. With two Wait States. 0.06
Power Consumption
Conditions Consumption 0.02 0.83 0.73 0.20 0.24 0.16 mW/MHz Unit
Table 4-2.
Peripheral PIO Controller
Power Consumption per Peripheral
Consumption 15.3 15.0 W/MHz 36.3 27.8 Unit
Timer/Counter Channel Timer/Counter Block (3 Channels) USART
4.1
4.1.1
Thermal and Reliability Considerations
Thermal Data In Table 4-3, the device lifetime is estimated with the MIL-217 standard in the "moderately controlled" environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section "Junction Temperature" on page 5.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones.
4
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
Table 4-3. MTBF Versus Junction Temperature
Estimated Lifetime (MTBF) (Year) 10 5 3 2 Junction Temperature (TJ) (C) 100 125 150 175
Table 4-4 summarizes the thermal resistance data related to the package of interest. Table 4-4.
Symbol JA JC
Thermal Resistance Data
Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Package TQFP100 TQFP100 Typ 40 C/W 6.4 Unit
4.1.2
Reliability Data The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 4-5.
Parameter Number of Logic Gates Number of Memory Gates Device Die Size
Reliability Data
Data 280 12,897 21.2 Unit K gates K gates mm2
4.2
Junction Temperature
The average chip-junction temperature TJ in C can be obtained from the following: 1. 2. T J = T A + ( P D x JA )
T J = T A + ( P D x ( HEATSINK + JC ) )
Where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 4-4 on page 5. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 4-4 on page 5. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 4. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C
5
1795E-ATARM-12-Dec-05
5. Conditions
5.1 Timing Results
The delays are given as typical values in the following conditions: * VDDIO = 3.0V * VDDCORE = 1.8V * Ambient Temperature = 25 C * Load Capacitance = 0 pF * The output level change detection is 0.5 x VDDIO * The input level is 0.8V for a low-level detection and is 2.0V for a high level detection. The minimum and maximum values given in the AC characteristic tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used: t = T x ( VDDCORE x t DATASHEET ) + VDDIO x Where: * T is the derating factor in temperature given in Figure 5-1. * VDDCORE is the derating factor for the Core Power Supply given in Figure 5-2 on page 7. * tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. * VDDIO is the derating factor for the I/O Power Supply given in Figure 5-3 on page 8. * CSIGNAL is the capacitance load on the considered output pin.(1) * CSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max values in this datasheet. The input delays are given as typical values.
Note: The user must take into account the package capacitance load contribution (CIN) described in Table 3-1 on page 3.
( CSIGNAL x CSIGNAL )
6
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
5.2 Temperature Derating Factor
Figure 5-1. Derating Curve for Different Operating Temperatures
1.2
1.1
Derating Factor
1
Derating Factor for Typ Case is 1
0.9
0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160
Operating Temperature C
5.3
Core Voltage Derating Factor
Figure 5-2. Core Voltage Derating Factor
3
Derating Factor
2.5
Derating Factor for Typ Case is 1
2
1.5
1
0.5
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Core Supply Voltage (V)
7
1795E-ATARM-12-Dec-05
5.4
IO Voltage Derating Factor
Figure 5-3.
1.6 1.5 Derating Factor 1.4 1.3 1.2 1.1 1 0.9 0.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDDIO Voltage Level Derating Factor for Typ Case is 1
Derating Factor for Different VDDIO Power Supply Levels
8
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
6. Clock Waveforms
Table 6-1.
Symbol
Master Clock Waveform Parameters
Parameter Conditions Min Max Units
1/(tCP) tCP tCH tCL
Oscillator Frequency Oscillator Period High Half-period Low Half-period 12.2 5.0 5.5
82.1
MHz ns ns ns
Table 1. Clock Propagation Times
Symbol Parameter Conditions Min Max Units
tCDLH
Rising Edge Propagation Time
CMCKO = 0 pF CMCKO derating
4.4 0.199 4.5 0.153
6.6 0.295 6.7 0.228
ns ns/pF ns ns/pF
tCDHL
Falling Edge Propagation Time
CMCKO = 0 pF CMCKO derating
Figure 6-1.
Clock Waveform
tCH
MCKI
2.0V
2.0V 0.8V tCL tCP 0.8V 0.8V
MCKO
tCDLH
0.5 VDDIO
0.5 VDDIO
tCDHL
Table 6-2.
Symbol
NRST to MCKO
Parameter Min Max Units
tD
NRST Rising Edge to MCKO Valid Time
3(tCP/2)
7(tCP/2)
ns
9
1795E-ATARM-12-Dec-05
Figure 6-2.
NRST
MCKO Relative to NRST
tD
MCKO
10
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
7. AC Characteristics
7.1 EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in the section "Timing Results" on page 6. See Figure 7-1 on page 14.
Table 7-1.
Symbol
General-purpose EBI Signals
Parameter Conditions Min Max Units
EBI1
MCKI Falling to NUB Valid
CNUB = 0 pF CNUB derating
4.4 0.030 3.7 0.045 3.4 0.045 3.7 0.045 1.7 1.7
8.9 0.043 6.7 0.069 7.8 0.076 8.6 0.078
ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns
EBI2
MCKI Falling to NLB/A0 Valid
CNLB = 0 pF CNLB derating
EBI3
MCKI Falling to A1 - A23 Valid MCKI Falling to Chip Select Change NWAIT Setup before MCKI Rising NWAIT Hold after MCKI Rising
CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating
EBI4 EBI5 EBI6
Table 7-2.
Symbol
EBI Write Signals
Parameter Conditions Min Max Units
EBI7
MCKI Rising to NWR Active (No Wait States)
CNWR = 0 pF CNWR derating
3.9 0.029 4.4 0.029 3.8 0.029 4.2 0.029 4.2 0.045 3.1 0.030 3.1 0.043 2.9 0.043
6.3 0.043 7.0 0.043 6.3 0.044 6.7 0.044 7.5 0.080 7.0 0.043 5.4 0.073 7.0 0.076
ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF
EBI8
MCKI Rising to NWR Active (Wait States)
CNWR = 0 pF CNWR derating
EBI9
MCKI Falling to NWR Inactive (No Wait States)
CNWR = 0 pF CNWR derating
EBI10
MCKI Rising to NWR Inactive (Wait States)
CNWR = 0 pF CNWR derating
EBI11
MCKI Rising to D0 - D15 Out Valid
CDATA = 0 pF CDATA derating
EBI12
NWR High to NUB Change
CNUB = 0 pF CNUB derating
EBI13
NWR High to NLB/A0 Change
CNLB = 0 pF CNLB derating
EBI14
NWR High to A1 - A23 Change
CADD = 0 pF CADD derating
11
1795E-ATARM-12-Dec-05
Table 7-2.
Symbol
EBI Write Signals (Continued)
Parameter Conditions Min Max Units
EBI15
NWR High to Chip Select Inactive
CNCS = 0 pF CNCS derating C = 0 pF
2.9 0.052 tCH - 1.8 -0.080 0.044 n x tCP - 1.3 -0.080 0.044 2.2
(2)
6.8 0.067
ns ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns ns/pF ns ns/pF
EBI16
Data Out Valid before NWR High (No Wait States)(1)
CDATA derating CNWR derating C = 0 pF
EBI17
Data Out Valid before NWR High (Wait States)
(1)
CDATA derating CNWR derating
EBI18 EBI19
Data Out Valid after NWR High NWR Minimum Pulse Width (No Wait States)(1) CNWR = 0 pF CNWR derating NWR Minimum Pulse Width (Wait States)(1) 1. The derating factor should not be applied to tCH or tCP. 2. n = number of standard wait states inserted. CNWR = 0 pF CNWR derating
tCH - 0.6 0 n x tCP - 0.9(2) 0
EBI20 Notes:
Table 7-3.
Symbol
EBI Read Signals
Parameter Conditions Min Max Units
EBI21
MCKI Falling to NRD Active(1)
CNRD = 0 pF CNRD derating
4.5 0.029 3.8 0.029 4.1 0.030 3.9 0.030 1.5 1.2
7.9 0.043 7.3 0.043 6.5 0.044 5.8 0.044
ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns
EBI22
MCKI Rising to NRD Active(2)
CNRD = 0 pF CNRD derating
EBI23
MCKI Falling to NRD Inactive(1)
CNRD = 0 pF CNRD derating
EBI24 EBI25 EBI26 EBI27
MCKI Falling to NRD Inactive (2) D0 - D15 In Setup before MCKI Falling Edge(5) D0 - D15 In Hold after MCKI Falling Edge NRD High to NUB Change
(6)
CNRD = 0 pF CNRD derating
CNUB = 0 pF CNUB derating
3.2 0.030 3.2 0.043 2.8 0.043 2.9 0.052
7.1 0.043 4.6 0.073 6.1 0.076 6.2 0.067
ns ns/pF ns ns/pF ns ns/pF ns ns/pF
EBI28
NRD High to NLB/A0 Change
CNLB = 0 pF CNLB derating
EBI29
NRD High to A1 - A23 Change
CADD = 0 pF CADD derating
EBI30
NRD High to Chip Select Inactive
CNCS = 0 pF CNCS derating
12
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
Table 7-3.
Symbol
EBI Read Signals
Parameter Conditions Min Max Units
EBI31
Data Setup before NRD High(6)
CNRD = 0 pF CNRD derating
8.0 0.044 -3.1 -0.030 (n +1) tCP - 1.9(4) 0.001 n x tCP + (tCH - 1.5) 0.001
(4)
ns ns/pF ns ns/pF ns ns/pF ns ns/pF
EBI32
Data Hold after NRD High(6)
CNRD = 0 pF CNRD derating
EBI33
NRD Minimum Pulse Width(1) (3)
CNRD = 0 pF CNRD derating
EBI34 Notes:
NRD Minimum Pulse Width(2) (3) 1. Early Read Protocol. 2. Standard Read Protocol. 3. The derating factor should not be applied to tCH or tCP. 4. n = number of standard wait states inserted.
CNRD = 0 pF CNRD derating
5. Only one of these two timings, EB25 or EBI31, needs to be met. 6. Only one of these two timings, EB26 or EBI32, needs to be met.
Table 7-4.
Symbol
EBI Read and Write Control Signals. Capacitance Limitation
Parameter Conditions Min Max Units
TCPLNRD(1) TCPLNWR(2) Notes:
Master Clock Low Due to NRD Capacitance
CNRD = 0 pF CNRD derating
7.3 0.044 7.6 0.044
ns ns/pF ns ns/pF
Master CLock Low Due to NWR Capacitance
CNWR = 0 pF CNWR derating
1. If this condition is not met, the action depends on the read protocol intended for use. * Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. * Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed.
13
1795E-ATARM-12-Dec-05
Figure 7-1.
EBI Signals Relative to MCKI
MCKI EBI4 EBI4
NCS
CS EBI3 A1 - A23 EBI5 NWAIT EBI6
EBI1/EBI2 NUB/NLB/A0 EBI21 EBI33 EBI27-30
EBI23
NRD(1)
EBI22 NRD(2) EBI31
EBI24 EBI34 EBI32 EBI25 EBI26
D0 - D15 Read EBI7 NWR (No Wait States) EBI9 EBI19 EBI8 NWR (Wait States) EBI11 EBI16 D0 - D15 to Write No Wait Wait EBI18 EBI20 EBI17 EBI18 EBI10 EBI12-15
Notes:
1. Early Read Protocol. 2. Standard Read Protocol.
14
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
7.2
7.2.1
Peripheral Signals
USART Signals The inputs have to meet the minimum pulse width and period constraints shown in Table 7-5 and Table 7-6, and represented in Figure 7-2.
Table 7-5.
Symbol
USART Input Minimum Pulse Width
Parameter Min Pulse Width Units
US1
SCK/RXD Minimum Pulse Width
5(tCP/2)
ns
Table 7-6.
Symbol
USART Minimum Input Period
Parameter Min Input Period Units
US2
SCK Minimum Input Period
9(tCP/2)
ns
Figure 7-2.
USART Signals
US1
RXD US2 US1 SCK
7.2.2
Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Table 7-7 and Table 7-8, and as represented in Figure 73. Table 7-7.
Symbol
Timer Input Minimum Pulse Width
Parameter Min Pulse Width Units
TC1
TCLK/TIOA/TIOB Minimum Pulse Width
3(tCP/2)
ns
15
1795E-ATARM-12-Dec-05
Table 7-8.
Symbol
Timer Input Minimum Period
Parameter Min Input Period Units
TC2
TCLK/TIOA/TIOB Minimum Input Period
5(tCP/2)
ns
Figure 7-3.
Timer Input
TC2 3(tCP/2) 3(tCP/2)
MCKI TC1 TIOA/ TIOB/ TCLK
7.2.3
Reset Signals A minimum pulse width is necessary, as shown in Table 7-9 and as represented in Figure 7-4.
Table 7-9.
Symbol
Reset Minimum Pulse Width
Parameter Min Pulse-width Units
RST1
NRST Minimum Pulse Width
10(tCP)
ns
Figure 7-4.
Reset Signal
RST1
NRST
Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous. 7.2.4 Advanced Interrupt Controller Signals Inputs have to meet the minimum pulse width and minimum input period shown in Table 7-10 and Table 7-11 and represented in Figure 7-5.
16
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
Table 7-10.
Symbol
AIC Input Minimum Pulse Width
Parameter Min Pulse Width Units
AIC1
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width
3(tCP/2)
ns
Table 7-11.
Symbol
AIC Input Minimum Period
Parameter Min Input Period Units
AIC2
AIC Minimum Input Period
5(tCP/2)
ns
Figure 7-5.
AIC Signals
AIC2
MCKI AIC1 FIQ/IRQ0/ IRQ1/IRQ2/ IRQ3 Input
7.2.5
Parallel I/O Signals The inputs have to meet the minimum pulse width shown in Table 7-12 and represented in Figure 7-6.
Table 7-12.
Symbol
PIO Input Minimum Pulse Width
Parameter Min Pulse Width Units
PIO1
PIO Input Minimum Pulse Width
3(tCP/2)
ns
Figure 7-6.
PIO Signal
PIO1
PIO Inputs
17
1795E-ATARM-12-Dec-05
7.2.6
ICE Interface Signals
Table 7-13.
Symbol
ICE Interface Timing Specifications
Parameter Conditions Min Max Units
ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 ICE7 ICE8
NTRST Minimum Pulse Width NTRST High Recovery to TCK High NTRST High Removal from TCK High TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid CTDO = 0 pF CTDO derating
10.9 0.9 -0.3 23.5 22.7 46.1 0.4 0.4 3.3 0.001 7.4 0.28
ns ns ns ns ns ns ns ns ns ns/pF ns ns/pF
ICE9
Figure 7-7.
ICE Interface Signal
ICE0
NTRST ICE1 ICE5 TCK ICE3 ICE4 ICE2
TMS/TDI ICE6 ICE7
TDO ICE8 ICE9
18
AT91R40008
1795E-ATARM-12-Dec-05
AT91R40008
Revision History
Version
page
Comments
1795A 1795B page 2 page 2 page 3 page 3 page 9 1795C page 1 page 9 page 13 1795D page 6 page 9 1795E all page 9
10-Dec-01 First Issue
7-Aug-2002 Absolute Maximum Ratings: changed Table 1. DC Characteristics: changed Table 2. Power Consumption: changed Table 3. Power Consumption per Peripheral: changed Table 7. Master Waveclock Parameters: changed
24-Mar-2004
Features: Change to "Fully Static Operation" values. Figure 4. Clock Waveform: tR and tF removed, tCL measurement changed.
Table 12. Footnote 5 changed and footnote 6 added to clarify selection needs. 22-Oct-04
Change to Timing Results (CSR 04-320) Change to Table 7 and Figure 4 (CSR 04-320)
12-Dec-05
Reformatted in Atmel template version 5.2. Numbering properties are changed as a result. Table 6-1, "Master Clock Waveform Parameters," note deleted. (CSR 05-446)
19
1795E-ATARM-12-Dec-05
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) Atmel Corporation 2005. All rights reserved. Atmel(R), logo and combinations thereof, Everywhere You Are(R) and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM(R), the ARM Powered(R) logo, and others, are registered trademarks or trademarks of ARM Limited. Other terms and product names may be trademarks of others. Printed on recycled paper.
1795E-ATARM-12-Dec-05

▲Up To Search▲

Price & Availability of AT91R4000805

	To Download AT91R4000805 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .